Semiconductor memory

ABSTRACT

When a write &amp; auto precharge command is input into a chip, signals CPSRX and AUTPL are at “H”. After finishing a column operation, the level of the signal CPSRX shift to “L”. When CPSRX=“L” and AUTPL=“H”, if a signal CSLCK is at “H”, an auto precharge enable signal AUTPE is at “H”. The signal AUTPE is at “H” when the signal CSLCK is at “H”, and does not depend upon the leading edge of an external clock VCLK. Since auto precharge is executed from the time a column select line CSL is activated, the time the potential of a selected word line is shifted to a non-selection level can be kept constant irrespective of the frequency of the external clock.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2000-195173, filed Jun.28, 2000, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory, and moreparticularly, a synchronous DRAM that executes an auto prechargeoperation.

[0004] 2. Description of the Related Art

[0005] A synchronous DRAM (hereinafter referred to as an “SDRAM”) thatoperates in synchronism with an external clock has an operation modecalled “auto precharge (bank precharge)”.

[0006] In the auto precharge mode, in the memory chip of the DRAM, thepotential of a presently-selected word line in a bank automaticallyshifts to a non-selection potential (e.g. the ground potential), andpreparation processing for the next processing (for, for example,shifting the potential of a word line in the same bank to be selectednext to a selection potential), i.e. bank precharge, is executed.

[0007]FIG. 1 shows an essential part of a conventional SDRAM having theauto precharge mode.

[0008] In the structure shown in FIG. 1, in the write mode, a burstlength counter 12 is activated to thereby latch a burst signal and set acolumn select line enable signal CPSRX at “H”. When the level of thecolumn select line enable signal CPSRX rises to “H”, a column clockgenerator 13 is activated. The column clock generator 13 outputs acontrol signal CSLCK for controlling the potential of a column selectline CSL.

[0009] A clock CLKIN (=VCLK) is input to the column clock generator 13and an auto precharge shift register 15. After finishing the columnburst operation, the column select line enable signal CPSRX lowers to“L”.

[0010] When a write & auto precharge command is input to an inputreceiver/command decoder 11, an auto precharge signal AUTPL is input toan auto precharge decoder 14. The auto precharge decoder 14, in turn,generates an auto precharge enable signal AUTPE based on the columnselect line enable signal CPSRX and the auto precharge signal AUTPL.

[0011] The auto precharge enable signal AUTPE is input to the autoprecharge shift register 15, where it is shifted by tWR in synchronismwith the clock CLKIN and output as a signal AUTPG. A bank controller 16outputs a bank precharge signal BNK based on the signal AUTPG. As aresult, bank precharge is executed, and the potential WL of apresently-selected word line is shifted from the selection potential toa non-selection potential.

[0012]FIG. 2 illustrates a concrete example of the auto prechargedecoder 14 appearing in FIG. 1. The auto precharge decoder 14 comprisesinverters 11 and 12 and a NAND circuit NA1. Further, FIGS. 3A and 3Billustrate a concrete example of the auto precharge shift register 15appearing in FIG. 1.

[0013]FIG. 4 shows signal waveforms in the write & auto precharge mode.

[0014] The auto precharge mode is provided in, for example, a doubledata rate (DDR) type SDRAM.

[0015] In the write operation of the DDR type SDRAM, data VDQ is notinput into the chip in synchronism with a command cycle, but apredetermined clock cycle is necessary until the data is started to beinput after the command cycle finishes. This is called “write latency(hereinafter referred to as “WCL”)”. In the waveforms of FIG. 4, WCL isset at 1.

[0016] Further, in the DDR type SDRAM, when inputting the data VDQ intothe chip, a dedicated input trigger, called “DQS (=VDQS)”, is used.Specifically, the data VDQ is input into the chip in synchronism withthe edges of the trigger DQS. Further, the trigger DQS usually has aphase shift from an external clock VCLK. This phase shift is called a“DQS skew”. In the waveforms in FIG. 4, the DQS skew is set at 0.

[0017] In the write operation, data is input into the chip, and then thepotential of the column select line CSL is raised, thereby writing thedata into the memory cells of a selected column. For this reason, whenwriting a plurality of continuously input data items into memory cells,a predetermined time period is required after all the data items areinput to the chip until the last data item is actually written into amemory cell.

[0018] To secure the predetermined time period, a write recovery timetWR is prepared. The write recovery time tWR is the period of time thatelapses from the time the first external clock pulse signal occursimmediately after the input of the last data item into the chip, to thetime the next external clock pulse occurs. In the DDR type SDRAM, thebank precharge command is not allowed to be input into the chip untilsaid next external clock pulse occurs.

[0019] This is because if the bank precharge command is input into thechip before the write recovery time tWR elapses, bank precharge isstarted and the potential of the presently-selected work line WL shiftsto the non-selection level, for the next operation, before the last dataitem is written into a memory cell, resulting in a write error.

[0020] The process of setting the write recovery time tWR is, of course,required even in the write & auto precharge mode in which no prechargecommand is needed.

[0021] In the write & auto precharge mode, the auto precharge enablesignal AUTPE is shifted by tWR using the external clock VCLK (=CLKIN),thereby executing bank precharge and shifting the potential of thepresently-selected work line WL to the non-selection level for the nextoperation after the last data item is written into the chip.

[0022] The above operation will be described in more detail. First, whena bank active command BA is input, the level of a bank active signal BNKrises to “H”, thereby raising the potential of a word line WL selectedby a row address signal. Subsequently, a write command WT is input,whereby a burst enable signal CPSRX is activated, i.e. rises to “H”,after a number of pulses of the external clock corresponding to thewrite latency WCL are output. As a result, an operation for columnselection is started.

[0023] More specifically, when the burst enable signal CPSRX is at “H”,the external clocks VCLK and DQS are input, whereby the column dedicatedclock CSLCK rises to “H” to activate the column decoder. Consequently,the potential of the column select line CSL is raised on the basis of acolumn address signal, thereby writing data into a memory cell selectedby the selected column.

[0024] After the last one of continuous data items having apredetermined burst length is written into a memory cell, bank prechargeis executed and the potential of the presently-selected word line WL islowered, in preparation for the next processing (for, for example,shifting the potential of a word line in the same bank to be selectednext to the selection potential).

[0025] In the waveforms of FIG. 4, since tWR=1, the potential of theword line WL is lowered when one pulse of the external clock has risenafter the rising of one pulse of the external clock immediately afterthe last data item is input into the chip.

[0026] In order to write all the continuous data items of thepredetermined burst length into memory cells, the time Δt1 required fromthe rising of the potential of the column select line CSL to the fallingof that of the selected word line WL must be greater than the time Δt2required from the rising of the potential of the column select line CSLto the writing of all the data items into the memory cells, as is shownin FIG. 5.

[0027] When Δt1>Δt2, the difference Δt3 therebetween acts as a marginfor the time required for writing data into the memory cells.

[0028] In general, in the waveforms shown in FIG. 5, the number of clockpulses defines tWR. If the number of clock pulses that define tWR isconstant (e.g. 1), the faster the transistors operate or the higher thefrequency of the external clock, the shorter Δt1 is.

[0029] However, Δt2 is the time necessary to write all data into thememory cells, and hence significantly depends upon the capacity andresistance, etc. of bit lines BL or the memory cells. Accordingly, evenwhen the transistors operate at high speed or the frequency of theexternal clock is high, Δt2 is not as shortened as Δt1.

[0030] This being so, the margin Δt3 for the time required to write datainto memory cells becomes very short. In some cases, Δt3 disappears andΔt2 is greater than Δt1, thereby causing a write error, as is shown inFIG. 6.

[0031] Furthermore, in a DDR type SDRAM having the signal DQS, it ispossible that a skew of “Δt4” may occur between the data input signalVDQS (=DQS) and the external clock VCLK (=CLKIN) as shown in FIG. 7.

[0032] Since the column select line CSL is activated in synchronism withthe signal DQS, if the signal DQS delays from the external clock VCLK,the column select line CSL is activated after a period of timecorresponding to the delay of the signal DQS elapses. Accordingly, thetime required for writing data into memory cells is lengthened.

[0033] The point of time at which the potential of the selected wordline WL is lowered corresponds to the rising time of the external clockVCLK, and hence is always constant. Accordingly, it is possible that thetime required for writing data into memory cells is lengthened, themargin Δt3 disappears, and Δt2 becomes greater than Δt1, thereby causinga write error, as is shown in FIG. 7.

[0034] To prevent the write error, a method could be devised where thenumber of clock pulses for determining tWR is increased, for example,from 1 to 2, as is shown in FIG. 8. In this case, since the point oftime at which the level of the signal AUTPG rises to “H” delays, thetime Δt1 is lengthened which is required until the potential of the wordlines is lowered after the potential of the column line CSL is raised.Accordingly, the difference Δt3 between Δt1 and Δt2 (required until datais written into memory cells after the potential of the column selectline CSL is raised) can be secured, thereby preventing write errors.

[0035] In the prior art, however, the above-mentioned measure, i.e.shifting the auto precharge enable signal AUTPE by two clock pulses,using the clock CLKIN, requires a big change in the circuit structure ofthe auto precharge shift register 15 shown in FIG. 1. In other words,the existing circuit (tWR corresponds to one clock pulse) cannot be usedwithout changes, and a lot of time is required to design and develop asuitable circuit.

BRIEF SUMMARY OF THE INVENTION

[0036] It is the object of the present invention to provide asemiconductor memory completely free from a write error without changingthe number of clock pulses that defines a write recovery time tWR (i.e.without a big change in circuit structure), even if the transistorsincorporated therein are designed to operate at higher speeds and/or thefrequency of an external clock is increased.

[0037] To attain the object, there is provided a semiconductor memorycomprising: a generator for generating a pulse signal, used to operate acolumn decoder, on the basis of a clock signal and a first controlsignal; a precharge decoder for outputting a second control signal, usedto control an operation of a row decoder, on the basis of the firstcontrol signal and the pulse signal; and a delay circuit operableindependent of the clock signal for delaying the second control signalby a predetermined time period.

[0038] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0039] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently embodimentsof the invention, and together with the general description given aboveand the detailed description of the embodiments given below, serve toexplain the principles of the invention.

[0040]FIG. 1 is a block diagram illustrating a conventional circuit forexecuting a write & precharge operation;

[0041]FIG. 2 is a circuit diagram illustrating a conventional autoprecharge decoder;

[0042]FIGS. 3A and 3B are circuit diagrams illustrating a conventionalauto precharge shift register;

[0043]FIG. 4 is a view of signal waveforms used to execute aconventional write & auto precharge operation;

[0044]FIG. 5 is a view of signal waveforms used to execute aconventional write & auto precharge operation;

[0045]FIG. 6 is a view of signal waveforms obtained when the frequencyof a clock is increased in FIG. 4;

[0046]FIG. 7 is a view of signal waveforms obtained when a signal DQSdelays in FIG. 4;

[0047]FIG. 8 is a view of signal waveforms obtained when tWR correspondsto two clock pulses in FIG. 6;

[0048]FIG. 9 is a block diagram illustrating a circuit for executing awrite & auto precharge operation incorporated in the present invention;

[0049]FIG. 10 is a view illustrating a first example of a circuit forcreating a signal CSLCK;

[0050]FIG. 11 is a view illustrating a second example of the circuit forcreating the signal CSLCK;

[0051]FIG. 12 is a view illustrating a third example of the circuit forcreating the signal CSLCK;

[0052]FIG. 13 is a view illustrating an example of an auto prechargedecoder;

[0053]FIG. 14 is a view illustrating a first example of an autoprecharge delay circuit;

[0054]FIG. 15 is a view illustrating a second example of the autoprecharge delay circuit;

[0055]FIG. 16 is a view of signal waveforms used in a first example ofthe present invention;

[0056]FIG. 17 is a view of signal waveforms used in a second example ofthe present invention;

[0057]FIG. 18 is a view of signal waveforms used in a third example ofthe present invention; and

[0058]FIG. 19 is a view of signal waveforms used in a fourth example ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0059] A semiconductor memory according to the present invention will bedescribed in detail with reference to the accompanying drawings.

Outline

[0060] The present invention is characterized in that a clock CSLCK foractivating a column select line CSL is used as a signal for starting anauto precharge operation, and the leading edge of an external clockpulse is not used to start the auto precharge operation. Furthermore, inthe present invention, an auto precharge delay circuit is used toexecute auto precharge control, in place of the conventional autoprecharge shift register (denoted by reference numeral 15 in FIG. 1).

[0061] Auto precharge (bank precharge) is arranged to be executed inpreparation of the next operation when the column select line CSL hasshifted to its active state (CSLCK=“H”). Further, the auto prechargedelay circuit is used to adjust the point of time at which the potentialof a selected word line is shifted to its non-selection potential (islowered). As a result, the point of time at which the potential of theword lines is lowered (WL=“L”) does not depend upon the frequency of anexternal clock VCLK but is kept constant. In other words, the potentialof the word lines is always lowered after the writing of data intomemory cells is completed.

[0062]FIG. 9 shows an essential part of an SDRAM having an autoprecharge mode and according to the present invention.

[0063] In the write mode, a burst length counter 12 is activated tothereby latch a burst signal and set a column select line enable signalCPSRX at “H”. When the level of the column select line enable signalCPSRX rises to “H”, a column clock generator 13 is activated. The columnclock generator 13 outputs a control signal CSLCK for controlling thepotential of a column select line CSL.

[0064] A clock CLKIN (=VCLK) is input to the column clock generator 13but not to an auto precharge delay circuit 17 that is provided in placeof the conventional auto precharge shift register 15. After finishingthe column burst operation, the column select line enable signal CPSRXlowers to “L”.

[0065] When a write & auto precharge command is input to an inputreceiver/command decoder 11, an auto precharge signal AUTPL is input toan auto precharge decoder 14′. The auto precharge decoder 14′, in turn,generates an auto precharge enable signal AUTPE based on the controlsignal CSLCK and the auto precharge signal AUTPL.

[0066] The auto precharge enable signal AUTPE is input to the autoprecharge delay circuit 17, where it is shifted by tWR and output as acontrol signal AUTPG. A bank controller 16 outputs a bank prechargesignal BNK based on the control signal AUTPG. As a result, bankprecharge is executed, and the potential WL of the presently-selectedword line is lowered.

[0067] FIGS. 10-12 illustrate a concrete example of circuits forgenerating the control signal CSLCK supplied to the auto prechargedecoder 14′ appearing in FIG. 9. However, in place of using the circuitsshown in FIGS. 10-12, the output signal CSLCK of the column clockgenerator 13 shown in FIG. 9 may be input to the auto precharge decoder14′.

[0068]FIG. 13 shows a concrete example of the auto precharge decoder14′. The auto precharge decoder 14′ comprises inverters 13 and 14, aNAND circuit NA12 and a NOR circuit NR1. Further, FIGS. 14 and 15illustrate concrete examples of the auto precharge delay circuit 17appearing in FIG. 9.

FIRST EXAMPLE

[0069]FIG. 16 shows signal waveforms used in the write & auto prechargemode in a first example of the present invention.

[0070] Referring now to FIGS. 9 and 16, the operation of the firstexample will be described.

[0071] In the first example, a clock is used to input data into thechip, and no DQS signal is used. Accordingly, a control pulse signalCSLCK for activating the column select line CSL is created insynchronism with the trailing edge of the clock CLKIN (=VCLK). The pulsesignal input to the auto precharge decoder 14′ is generated by, forexample, a pulse generator as shown in FIG. 10.

[0072] When the write & auto precharge command is input to the chip, thecolumn select line enable signal CPSRX and the auto precharge signalAUTPL assume their active states (“H”), as in the conventional case.After finishing the column burst operation, the column select lineenable signal CPSRX lowers to “L”, as in the conventional case.

[0073] When CPSRX=“L” and AUTPL=“H”, if CSLCK=“H”, the level of theoutput signal (auto precharge enable signal) AUTPE of the auto prechargedecoder 14′ shown in FIGS. 9 and 13 rises to “H”. Thus, in the presentinvention, the level of the auto precharge enable signal for startingauto precharge rises to “H” if the level of the control signal CSLCKrises to “H”. In other words, the point of time at which the level ofthe auto precharge enable signal rises to “H” does not depend upon theleading edge of the external clock VCLK, unlike the conventional case.

[0074] The auto precharge enable signal AUTPE (=“H”) is delayed by apredetermined period by the auto precharge delay circuit shown in FIGS.14 or 15, and then output as a control signal AUTPG (=“H”). The bankcontroller 16 outputs a bank precharge signal BNK based on the controlsignal AUTPG. As a result, bank precharge is started and the potentialof a selected word line WL is lowered.

[0075] The period of time delayed by the auto precharge delay circuit 17shown in FIG. 9 (specifically shown in FIGS. 14 or 15) is determined onthe basis of the relationship between the time required until data issubstantially written into memory cells after the column select line CSLis activated, and the time required until the potential of the selectedword line is lowered after the start of the bank precharge operation.

[0076] Although, in this example, even when the frequency of theexternal clock is high, the column select line CSL is kept in the activestate. Accordingly, bank precharge is started and the potential of theselected word line WL is lowered, after data is substantially writteninto memory cells. For this reason, no write error will occur.

[0077] Furthermore, when the frequency of the external clock is high,the number of clock pulses that define the write recovery time tWR isincreased (see FIG. 8) as in the conventional case. However, even inthis case, no circuit for shifting the auto precharge enable signalAUTPE in synchronism with the clock is necessary. This means that it issufficient if the existing auto precharge delay circuit is used, andtherefore the time required for designing and developing thesemiconductor memory can be shortened.

SECOND EXAMPLE

[0078]FIG. 17 shows signal waveforms used in the write & auto prechargemode in a second example of the present invention.

[0079] Referring to FIGS. 9 and 17, the operation of the second examplewill be described.

[0080] The second example is directed to a semiconductor memory in whichdata is input into the chip in synchronism with the DQS signal thatdelays from the clock. The pulse signal CSLCK to be input to the autoprecharge decoder 14′ is generated by a pulse generator as shown in FIG.11.

[0081] When the write & auto precharge command is input to the chip, thecolumn select line enable signal CPSRX and the auto precharge signalAUTPL assume their active states (“H”) as in the conventional case.After finishing the column burst operation, the column select lineenable signal CPSRX lowers to “L”, as in the conventional case. Further,in this example, since data is input into the chip in synchronism withthe DQS signal, the control signal CSLCK is raised to “H” by the pulsegenerator shown in FIG. 11 when the DQS signal has been lowered.

[0082] When CPSRX=“L” and AUTPL=“H”, if CSLCK=“H”, the level of theoutput signal (auto precharge enable signal) AUTPE of the auto prechargedecoder 14′ shown in FIGS. 9 and 13 rises to “H”. Thus, in the presentinvention, the auto precharge enable signal for starting auto prechargerises to “H” if the control signal CSLCK rises to “H”. In other words,the point of time at which the auto precharge enable signal rises to “H”does not depend upon the leading edge of the external clock VCLK, unlikethe conventional case.

[0083] The auto precharge enable signal AUTPE (=“H”) is delayed by apredetermined period by the auto precharge delay circuit shown in FIGS.14 or 15, and then output as a control signal AUTPG (=“H”). The bankcontroller 16 outputs a bank precharge signal BNK based on the controlsignal AUTPG. As a result, bank precharge is started and the potentialof a selected word line WL is lowered.

[0084] In this example, if a skew of Δt4 exists between the clock VCLK(=CLKIN) and the signal VDQS (=DQS), and the signal DQS delays by Δt4from the clock VCLK, the pulse signal CSLCK also delays by Δt4.

[0085] In the conventional case, the skew Δt4 causes the potential of aselected word line WL to lower before data is not substantially writteninto memory cells.

[0086] In the present invention, however, the bank precharge enablesignal AUTPE is output on the basis of the pulse signal CSLCK.Therefore, if the pulse signal CSLCK delays by Δt4, the control signalAUTPG also delays by Δt4. As a result, bank precharge is started and thepotential of the selected word line WL is lowered, after the final burstdata is substantially written into a memory cell. This means that nowrite error will occur.

[0087] The period of time delayed by the auto precharge delay circuit 17shown in FIG. 9 (specifically shown in FIGS. 14 or 15) is determined onthe basis of the relationship between the time required until data issubstantially written into memory cells after the column select line CSLis activated, and the time required until the potential of the selectedword line is lowered after the start of the bank precharge operation.

[0088] In this example, even when a skew exists between the clock VCLK(=CLKIN) and the signal VDQS (=DQS), and the signal DQS delays from theclock VCLK, the time required until the potential of apresently-selected word line WL is lowered after the final data iscompletely written is kept constant. This means that the potential ofthe selected word line WL is always lowered after data is substantiallywritten into memory cells. Thus, even when such a skew exits, no writeerror will occur.

THIRD EXAMPLE

[0089]FIG. 18 shows signal waveforms used in the write & auto prechargemode in a third example of the present invention.

[0090] Referring to FIGS. 9 and 18, the operation of the third examplewill be described.

[0091] The third example is directed to a semiconductor memory in whichthe pulse signal CSLCK is activated when the signal DQS=“L” and theclock VCLK=“L”. In this example, if the signal DQS is input earlier thanor at the same time as the clock, the pulse signal CSLCK assumes “H”since VCLK=“L”. On the other hand, if the signal DQS is input later thanthe clock, the pulse signal CSLCK assumes “H” since DQS=“L”.

[0092] The pulse signal CSLCK to be input to the auto precharge decoder14′ is generated by a pulse generator as shown in FIG. 12.

[0093] When the write & auto precharge command is input to the chip, thecolumn select line enable signal CPSRX and the auto precharge signalAUTPL assume their active states (“H”) as in the conventional case.After finishing the column burst operation, the column select lineenable signal CPSRX lowers to “L”, as in the conventional case. Further,in this example, since data is input into the chip in synchronism withthe DQS signal, the control signal CSLCK is raised to “H” by the pulsegenerator shown in FIG. 11 when the DQS signal has been lowered.

[0094] When CPSRX=“L” and AUTPL=“H”, if CSLCK=“H”, the output signal(auto precharge enable signal) AUTPE of the auto precharge decoder 14′shown in FIGS. 9 and 13 rises to “H”. Thus, in the present invention,the auto precharge enable signal for starting auto precharge rises to“H” if the control signal CSLCK rises to “H”. In other words, the pointof time at which the auto precharge enable signal rises to “H” does notdepend upon the leading edge of the external clock VCLK, unlike theconventional case.

[0095] The auto precharge enable signal AUTPE (=“H”) is delayed by apredetermined period by the auto precharge delay circuit shown in FIGS.14 or 15, and then output as a control signal AUTPG (=“H”). The bankcontroller 16 outputs a bank precharge signal BNK based on the controlsignal AUTPG. As a result, bank precharge is started and the potentialof the selected word line WL is lowered.

[0096] In this example, if the signal DQS delays by Δt4 from the clockVCLK (=CLKIN), the pulse signal CSLCK also delays by Δt4, andaccordingly no write error will occur, as in the second example.

[0097] The period of time delayed by the auto precharge delay circuit 17shown in FIG. 9 (specifically shown in FIGS. 14 or 15) is determined onthe basis of the relationship between the time required until data issubstantially written into memory cells after the column select line CSLis activated, and the time required until the potential of the selectedword line is lowered after the start of the bank precharge operation.

[0098] This example can provide the same advantage as the secondexample. That is, even when a skew exists between the clock VCLK(=CLKIN) and the signal VDQS (=DQS), and the signal DQS delays from theclock VCLK, the time required until the potential of apresently-selected word line WL is lowered after the final data iscompletely written is kept constant. This means that the potential ofthe selected word line WL is always lowered after data is substantiallywritten into memory cells. Thus, even when such a skew exits, no writeerror will occur.

FOURTH EXAMPLE

[0099]FIG. 19 shows signal waveforms used in the write & auto prechargemode in a fourth example of the present invention.

[0100] Referring now to FIGS. 9 and 19, the operation of the fourthexample will be described.

[0101] The fourth example is directed to a semiconductor memory in whichonly the “H” level of a clock is used to input data into the chip, as inthe conventional SDRAM. In this example, WCL=0.

[0102] When the write & auto precharge command is input to the chip, thecolumn select line enable signal CPSRX and the auto precharge signalAUTPL assume their active states (“H”), as in the conventional case.After finishing the column burst operation, the column select lineenable signal CPSRX lowers to “L”, as in the conventional case. Also, inthis example, the control signal CSLCK rises to “H” in synchronism withthe “H” level of the clock.

[0103] When CPSRX=“L” and AUTPL=“H”, if CSLCK=“H”, the output signal(auto precharge enable signal) AUTPE of the auto precharge decoder 14′shown in FIGS. 9 and 13 rises to “H”. Thus, in the present invention,the auto precharge enable signal for starting auto precharge rises to“H” if the control signal CSLCK rises to “H”. In other words, the pointof time at which the auto precharge enable signal rises to “H” does notdepend upon the leading edge of the external clock VCLK, unlike theconventional case.

[0104] The auto precharge enable signal AUTPE (=“H”) is delayed by apredetermined period by the auto precharge delay circuit shown in FIGS.14 or 15, and then output as a control signal AUTPG (=“H”). The bankcontroller 16 outputs a bank precharge signal BNK based on the controlsignal AUTPG. As a result, bank precharge is started and the potentialof a selected word line WL is lowered.

[0105] The period of time delayed by the auto precharge delay circuit 17shown in FIG. 9 (specifically shown in FIGS. 14 or 15) is determined onthe basis of the relationship between the time required until data issubstantially written into memory cells after the column select line CSLis activated, and the time required until the potential of the selectedword line is lowered after the start of the bank precharge operation.

[0106] Although, in this example, even when the frequency of theexternal clock is high in a single-data type SDRAM, the column selectline CSL is kept in the active state. Accordingly, bank precharge isstarted and the potential of the selected word line WL is lowered, afterdata is substantially written into memory cells. For this reason, nowrite error will occur.

[0107] Furthermore, when the frequency of the external clock is high,the number of clock pulses that define the write recovery time tWR isincreased (see FIG. 8) as in the conventional case. However, even inthis case, no circuit for shifting the auto precharge enable signalAUTPE in synchronism with the clock is necessary. This means that it issufficient if the existing auto precharge delay circuit is used, andtherefore the time required for designing and developing thesemiconductor memory can be shortened.

Advantages of the Invention

[0108] As described above, the write recovery time tWR can be set sothat it does not depend upon the clock, and write errors can beprevented without changing the circuit structure even when a clock of ahigher frequency is used. Moreover, in the case of an SDRAM using theDQS signal, write errors due to delay of the DQS signal can be avoided.

[0109] Thus, in the present invention, bank precharge is started in thewrite & auto precharge mode, without making it depending upon the clock,when the write recovery time tWR has elapsed after the column operation.This also enables the semiconductor memory to be compatible, withoutchanging its circuit, with a clock of a higher frequency in the futureand with an according increase in the number of clock pulses that definethe write recovery time tWR.

[0110] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor memory comprising: a generatorfor generating a pulse signal, used to operate a column decoder, on thebasis of a clock signal and a first control signal; a precharge decoderfor outputting a second control signal, used to control an operation ofa row decoder, on the basis of the first control signal and the pulsesignal; and a delay circuit operable independent of the clock signal fordelaying the second control signal by a predetermined time period. 2.The semiconductor memory according to claim 1, wherein when the firstcontrol signal is activated, the pulse signal is generated from thegenerator, and when the first control signal is not activated, thesecond control signal is activated, and a potential of a selected wordline is at a non-selection level.
 3. The semiconductor memory accordingto claim 2, wherein the precharge decoder receives a third controlsignal, and the second control signal is activated when the thirdcontrol signal is activated.
 4. The semiconductor memory according toclaim 3, wherein the third control signal is activated in an autoprecharge mode, in which data is written into memory cells connected tothe selected word line, and then the potential of the selected word linehas the non-selection level and bank precharge is started.
 5. Thesemiconductor memory according to claim 2, wherein the potential of theselected word line has the non-selected level, irrespective of the clocksignal, when a predetermined time period has elapsed after the pulsesignal is output.
 6. The semiconductor memory according to claim 1,wherein the clock signal is input to the generator and not to the delaycircuit.
 7. The semiconductor memory according to claim 1, furthercomprising a burst length counter to be activated in a write mode,thereby latching a burst signal and outputting the first control signal.8. The semiconductor memory according to claim 7, wherein the firstcontrol signal is a column select line enable signal.
 9. Thesemiconductor memory according to claim 1, wherein the predeterminedtime period is equal to a write recovery time.
 10. The semiconductormemory according to claim 1, further comprising a bank controller foroutputting a bank precharge signal based on the second control signal,and wherein when the bank precharge signal is input to the row decoder,bank precharge is executed and the potential of a selected word line hasa non-selection level.
 11. The semiconductor memory according to claim 1being a synchronous DRAM having a plurality of banks.